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CMOS ASYNCHRONOUS FIFO 65,536 x 9
Integrated Device Technology, Inc.
ADVANCED INFORMATION IDT7208
FEATURES:
* 65536 x 9 storage capacity * High-speed: 15ns access time * Low power consumption -- Active: 660mW (max.) -- Power-down: 44mW (max.) * Asynchronous and simultaneous read and write * Fully expandable in both word depth and width * Pin and functionally compatible with IDT720x family * Status Flags: Empty, Half-Full, Full * Retransmit capability * High-performance CMOS technology * Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
internal pointers that load and empty data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. Data is toggled in and out of the device through the use of the Write (W) and Read (R) pins. The device's 9-bit width provides a bit for a control or parity at the user's option. It also features a Retransmit (RT) capability that allows the read pointer to be reset to its initial position when RT is pulsed LOW. A Half-Full Flag is available in the single device and width expansion modes. The IDT7208 is fabricated using IDT's high-speed CMOS technology. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing, rate buffering, and other applications.
DESCRIPTION:
The IDT7208 is a monolithic dual-port memory buffer with
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS (D 0 -D 8)
W
WRITE CONTROL
*
WRITE POINTER
RAM ARRAY 65,536 x 9
READ POINTER
THREESTATE BUFFERS DATA OUTPUTS (Q 0 -Q 8)
*
RS
R
READ CONTROL
*
*
*
FLAG LOGIC
* *
EF FF
*
RESET LOGIC
FL/RT
XI
EXPANSION LOGIC
XO/HF
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-3274/1
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IDT7208 CMOS ASYNCHRONOUS FIFO 65,536 x 9
COMMERCIAL TEMPERATURE RANGES
W
D8 D3 D2 D1 D0
XI FF
Q3 Q8 GND NC
Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
P28-1
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Vcc D4 D5 D6 D7
FL/RT RS EF XO/HF
INDEX D2 D1 D0
XI FF
4
3 2
Q7 Q6 Q5 Q4 R
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Q4 Q5
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DIP TOP VIEW
PLCC TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TA TBIAS TSTG IOUT Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial -0.5 to + 7.0 0 to +70 -55 to +125 -55 to + 125 50 Unit V C C C mA
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCCC GND VIH
(1)
Parameter Commercial Supply Voltage Supply Voltage Input High Voltage Commercial Input Low Voltage Commercial
Min. 4.5 0 2.0 --
R
14 15 16 17 18 19 20
Q0 Q1 NC Q2
5 6 7 8 9 10 11 12 13
32 31 30
NC Vcc D4 D5
29 28 27 26 25 24 23 22 21
PIN CONFIGURATIONS
D3 D8
W
D6 D7 NC
FL/RT RS EF XO/HF
J32-1
1
Q7 Q6
Typ. 5.0 0 -- --
Max. 5.5 0 -- 0.8
Unit V V V V
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
VIL(1)
NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS FOR THE 7208
(Commercial: VCC = 5.0V10%, TA = 0C to +70C)
IDT7208 Commercial tA = 20, 25, 35 ns Symbol ILI(1) ILO
(2)
Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage IOH = -2mA Output Logic "0" Voltage IOL = 8mA Active Power Supply Current Standby Current (R=W=RS=FL/RT=VIH) Power Down Current (All Input = VCC - 0.2V)
Min. -1 -10 2.4 -- -- -- --
Typ. -- -- -- -- -- -- --
Max. 1 10 -- 0.4 120 8
(4)
Unit A A V V mA mA mA
VOH VOL ICC1 ICC2
(3) (3)
12
ICC3(L)(3)
NOTES: 1. Measurements with 0.4 VIN VCC. 2. R VIH, 0.4 VOUT VCC. 3. ICC measurements are made with outputs open (only capacitive loading). 4. Tested at f = 20MHz.
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IDT7208 CMOS ASYNCHRONOUS FIFO 65,536 x 9
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AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V 10%, TA = 0C to +70C)
Commercial 7208L20 Symbol fS tRC tA tRR tRPW tRLZ tWLZ tDV tRHZ tWC tWPW tWR tDS tDH tRSC tRS tRSS tRTR tRTC tRT tRTS tRSR tEFL tHFH, tFFH tRTF tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF tXOL tXOH tXI tXIR tXIS
NOTES: 1. 2. 3. 4. Timings referenced as in AC Test Conditions. Pulse widths less than minimum are not allowed. Values guaranteed by design, not currently tested. Only applies to read data flow-through mode.
7208L25 Min. -- 35 -- 10 25 5 5 5 -- 35 25 10 15 0 35 25 25 10 35 25 25 10 -- -- -- -- -- 25 -- -- -- -- 25 -- -- 25 10 10 Max. 28.5 -- 25 -- -- -- -- -- 18 -- -- -- -- -- -- -- -- -- -- -- -- -- 35 35 35 25 25 -- 25 25 35 35 -- 25 25 -- -- --
7208L35 Min. -- 45 -- 10 35 5 10 5 -- 45 35 10 18 0 45 35 35 10 45 35 35 10 -- -- -- -- -- 35 -- -- -- -- 35 -- -- 35 10 15 Max. 22.2 -- 35 -- -- -- -- -- 20 -- -- -- -- -- -- -- -- -- -- -- -- -- 45 45 45 30 30 -- 30 30 45 45 -- 35 35 -- -- -- Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameters Shift Frequency Read Cycle Time Access Time Read Recovery Time Read Pulse Width(2) Read LOW to Data Bus LOW(3) Write HIGH to Data Bus Low-Z Data Valid from Read HIGH Read HIGH to Data Bus High-Z(3) Write Cycle Time Write Pulse Width(2) Write Recovery Time Data Set-up Time Data Hold Time Reset Cycle Time Reset Pulse Width(2) Reset Set-up Time(3) Reset Recovery Time Retransmit Cycle Time Retransmit Pulse Width(2) Retransmit Set-up Time(3) Retransmit Recovery Time Reset to EF LOW Reset to HF and FF HIGH Retransmit LOW to Flags Valid Read LOW to EF LOW Read HIGH to FF HIGH Read Pulse Width after EF HIGH Write HIGH to EF HIGH Write LOW to FF LOW Write LOW to HF Flag LOW Read HIGH to HF Flag HIGH Write Pulse Width after FF HIGH Read/Write LOW to XO LOW Read/Write HIGH to XO HIGH
XI XI XI
Min. -- 30 -- 10 20 5 5 5 -- 30 20 10 12 0 30 20 20 10 30 20 20 10 -- -- -- -- -- 20 -- -- -- -- 20 -- -- 20 10 10
(3, 4)
Max. 33.3 -- 20 -- -- -- -- -- 15 -- -- -- -- -- -- -- -- -- -- -- -- -- 30 30 30 20 20 -- 20 20 30 30 -- 20 20 -- -- --
Pulse Width(2) Recovery Time Set-up Time
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IDT7208 CMOS ASYNCHRONOUS FIFO 65,536 x 9
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AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figure 1
5V
1.1K D.U.T. 680 30pF*
CAPACITANCE(1) (TA = +25C, f = 1.0 MHz)
Symbol CIN(1) COUT
(1,2)
Parameter Input Capacitance Output Capacitance
Condition VIN = 0V VOUT = 0V
Max. 10 10
Unit pF pF
Figure 1. Output Load *Includes jig and scope capacitances.
OR EQUIVALENT CIRCUIT
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NOTES: 1. This parameter is sampled and not 100% tested. 2. With output deselected.
SIGNAL DESCRIPTIONS Inputs:
DATA IN (D0-D8) -- Data inputs for 9-bit wide data.
Controls:
RESET (RS -- Reset is accomplished whenever the Reset RS) (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place. Both the Read Enable (R) and Write Enable (W) inputs must R W be in the HIGH state during the window shown in Figure 2 (i.e. tRSS before the rising edge of RS and should not RS) change until tRSR after the rising edge of RS RS. WRITE ENABLE (W) -- A write cycle is initiated on the falling W edge of this input if the Full Flag (FF) is not set. Data set-up and hold times must be adhered-to, with respect to the rising edge of the Write Enable (W). Data is stored in the RAM array sequentially and independently of any on-going read operation. After half of the memory is filled, and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LOW, and will remain set until the difference between the write pointer and read pointer is less-than or equal to one-half of the total memory of the device. The Half-Full Flag (HF) is reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go LOW on the falling edge of the last write signal, which inhibits further write operations. Upon the completion of a valid read operation, the Full Flag (FF) will go HIGH after tRFF, allowing a new valid write to begin. When the FIFO is full, the internal write pointer is blocked from W, so external changes in W will not affect the FIFO when it is full.
READ ENABLE (R) -- A read cycle is initiated on the falling R edge of the Read Enable (R), provided the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis, independent of any ongoing write operations. After Read Enable (R) goes HIGH, the Data Outputs (Q0 through Q8) will return to a high-impedance condition until the next Read operation. When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, allowing the "final" read cycle but inhibiting further read operations, with the data outputs remaining in a highimpedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after tWEF and a valid Read can then begin. When the FIFO is empty, the internal read pointer is blocked from R so external changes will not affect the FIFO when it is empty. FIRST LOAD/RETRANSMIT (FL RT) -- This is a dualFL/RT purpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first device loaded (see Operating Modes). The Single Device Mode is initiated by grounding the Expansion In (XI). The IDT7208 can be made to retransmit data when the Retransmit Enable Control (RT) input is pulsed LOW. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. The status of the Flags will change depending on the relative locations of the read and write pointers. Read Enable (R) and Write Enable (W) must be in the HIGH state during retransmit. This feature is useful when less than 65,536 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode. EXPANSION IN (XI -- This input is a dual-purpose pin. XI) Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy-Chain Mode.
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IDT7208 CMOS ASYNCHRONOUS FIFO 65,536 x 9
COMMERCIAL TEMPERATURE RANGES
Outputs:
FULL FLAG (FF -- The Full Flag (FF) will go LOW, inhibiting FF) further write operations, when the device is full. If the read pointer is not moved after Reset (RS), the Full Flag (FF) will go LOW after 65,536 writes. EMPTY FLAG (EF -- The Empty Flag (EF) will go LOW, EF) inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. EXPANSION OUT/HALF-FULL FLAG (XO HF) -- This is a XO/HF dual-purpose output. In the single device mode, when Expansion In (XI) is grounded, this output acts as an indication of a halffull memory. After half of the memory is filled, and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LOW
and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. There will be an XO pulse when the Write pointer reaches the last location of memory, and an additional XO pulse when the Read pointer reaches the last location of memory. DATA OUTPUTS (Q0-Q8) -- Q0-Q8 are data outputs for 9bit wide data. These outputs are in a high-impedance condition whenever Read (R) is in a HIGH state.
t RSC t RS
RS
t RSS
W
t RSR
t RSS
R
t EFL
EF
t HFH , t FFH
HF, FF
NOTE: 1. W and R = VIH around the rising edge of RS. Figure 2. Reset
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t RC tA
R
t RPW t RR tA t DV DATA t WC
OUT
t RLZ Q 0 -Q 8
t RHZ DATA
OUT
VALID
VALID
t WPW
W
t WR
t DS D 0 -D 8 DATA
IN
t DH VALID DATA
IN
VALID
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Figure 3. Asynchronous Write and Read Operation
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IDT7208 CMOS ASYNCHRONOUS FIFO 65,536 x 9
COMMERCIAL TEMPERATURE RANGES
LAST WRITE
IGNORED WRITE
FIRST READ
R
W
tWFF
FF
tRFF
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Figure 4. Full FlagTiming From Last Write to First Read
LAST READ
IGNORED READ
FIRST WRITE
W
R
t REF
EF
t WEF
tA DATAOUT VALID
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Figure 5. Empty Flag Timing From Last Read to First Write
t
RT
RTC
t RT
t RTS
W,R
t RTR
RTF
HF, EF, FF
FLAG VALID
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NOTE: 1. EF, FF and HF may change status during Retransmit, but flags will be valid at tRTC. Figure 6. Retransmit
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IDT7208 CMOS ASYNCHRONOUS FIFO 65,536 x 9
COMMERCIAL TEMPERATURE RANGES
W
t WEF
EF
t RPE
R
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Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.
R
t
FF
RFF
t WPF
W
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse.
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W
tRHF
R
t WHF
HF
HALF-FULL OR LESS
MORE THAN HALF-FULL
HALF-FULL OR LESS
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Figure 9. Half-Full Flag Timing
W
WRITE TO LAST PHYSICAL LOCATION READ FROM LAST PHYSICAL LOCATION t XOL t XOH
R
t XOL
XO
t XOH
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Figure 10. Expansion Out
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IDT7208 CMOS ASYNCHRONOUS FIFO 65,536 x 9
COMMERCIAL TEMPERATURE RANGES
t
XI
XI
t XIR
t XIS
W
WRITE TO FIRST PHYSICAL LOCATION
t XIS READ FROM FIRST PHYSICAL LOCATION
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R
Figure 11. Expansion In
OPERATING MODES:
Care must be taken to assure that the appropriate flag is monitored by each system (i.e. FF is monitored on the device where W is used; EF is monitored on the device where R is used). Single Device Mode A single IDT7208 may be used when the application requirements are for 65,536 words or less. The IDT7208 is in a Single Device Configuration when the Expansion In (XI) control input is grounded (see Figure 12). Depth Expansion The IDT7208 can easily be adapted to applications when the requirements are for greater than 65,536 words. Figure 14 demonstrates Depth Expansion using three IDT7208s. Any depth can be attained by adding additional IDT7208s. The IDT7208 operates in the Depth Expansion mode when the following conditions are met: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (XI) pin of the next device. See Figure 14. 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all must be set to generate the correct composite FF or EF). See Figure 14. 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion Mode. tus flags (EF, FF and HF) can be detected from any one device. Figure 13 demonstrates an 18-bit word width by using two IDT7208s. Any word width can be attained by adding additional IDT7208s (Figure 13). Bidirectional Operation Applications which require data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing IDT7208s as shown in Figure 16. Both Depth Expansion and Width Expansion may be used in this mode. Data Flow-Through Two types of flow-through modes are permitted, a read flow-through and write flow-through mode. For the read flowthrough mode (Figure 17), the FIFO permits a reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising edge of W, called the first write edge, and it remains on the bus until the R line is raised from LOW-to-HIGH, after which the bus would go into a three-state mode after tRHZ ns. The EF line would have a pulse showing temporary deassertion and then would be asserted. In the write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO. The R line causes the FF to be deasserted but the W line being LOW causes it to be asserted again in anticipation of a new data word. On the rising edge of W, the new word is loaded in the FIFO. The W line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write pointer. Compound Expansion The two expansion techniques described above can be applied together in a straightforward manner to achieve large FIFO arrays (see Figure 15).
USAGE MODES:
Width Expansion Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Sta-
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IDT7208 CMOS ASYNCHRONOUS FIFO 65,536 x 9
COMMERCIAL TEMPERATURE RANGES
(HALF-FULL FLAG) WRITE (W) 9 DATA IN (D) FULL FLAG (FF) RESET (RS)
(HF) READ (R) IDT 7208 9 DATA OUT (Q) EMPTY FLAG (EF) RETRANSMIT (RT)
EXPANSION IN (XI)
Figure 12. Block Diagram of 65,536 x 9 FIFO Used in Single Device Mode
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HF
HF
18 DATA IN (D) WRITE (W)
9
9
IDT 7208 FULL FLAG (FF) RESET (RS) 9
IDT 7208
READ (R) EMPTY FLAG (EF)
9
RETRANSMIT (RT)
XI
XI
18 DATA
OUT (Q)
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NOTE: 1. Flag detection is accomplished by monitoring the FF, Do not connect any output signals together.
EF
and HF signals on either (any) device used in the width expansion configuration.
Figure 13. Block Diagram of 65,536 x 18 FIFO Memory Used in Width Expansion Mode
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IDT7208 CMOS ASYNCHRONOUS FIFO 65,536 x 9
COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES TABLE I - RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Inputs Mode Reset Retransmit Read/Write
RS RT XI
Internal Status Read Pointer Location Zero Location Zero Increment (1) Write Pointer Location Zero Unchanged Increment (1)
EF
Outputs
FF HF
0 1 1
X 0 1
0 0 0
0 X X
1 X X
1 X X
7208 tbl 07
NOTE: 1. Pointer will Increment if flag is HIGH.
TABLE II - RESET AND FIRST LOAD
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs Mode Reset First Device Reset all Other Devices Read/Write
RS FL XI
Internal Status Read Pointer Location Zero Location Zero X Write Pointer Location Zero Location Zero X
EF
Outputs
FF
0 0 1
0 1 X
(1) (1) (1)
0 0 X
1 1 X
7208 tbl 08 NOTES: 1. XI is connected to XO of previous device. See Figure 14. 2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output
XO W FF
IDT 7208
R EF
D
9
9
FL
9
Q VCC
XI XO FF
FULL
9
IDT 7208
EF
EMPTY
FL
XI XO FF EF
9
RS
IDT 7208
FL XI
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Figure 14. Block Diagram of 196,608 x 9 FIFO Memory (Depth Expansion)
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IDT7208 CMOS ASYNCHRONOUS FIFO 65,536 x 9
COMMERCIAL TEMPERATURE RANGES
Q 0 -Q 8
Q 9 -Q 17 ***
Q (N-8)
-Q N
Q 0 -Q 8 IDT7208 DEPTH EXPANSION BLOCK
R, W, RS
Q 9 -Q 17 IDT7208 DEPTH EXPANSION BLOCK ***
Q (N-8) IDT7208 DEPTH EXPANSION BLOCK
-Q N
D 0 -D 8 D 0 -D N
NOTES: 1. For depth expansion block see section on Depth Expansion and Figure 14. 2. For Flag detection see section on Width Expansion and Figure 13.
D 9 -D 17 *** D 9 -D N D 18 -D N D (N-8) -D N
D (N-8) -D N
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Figure 15. Compound FIFO Expansion
WA
FF A
IDT 7208 IDT 7201A
RB EFB HF B
D A 0-8
Q B 0-8
SYSTEM A
SYSTEM B
Q A 0-8
RA HFA EF A
D B 0-8
IDT 7208
WB
FF B
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Figure 16. Bidirectional FIFO Operation
DATA IN
W
t RPE
R
EF
t WEF t WLZ DATA OUT tA
t REF DATA VALID
OUT
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Figure 17. Read Data Flow-Through Mode
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IDT7208 CMOS ASYNCHRONOUS FIFO 65,536 x 9
COMMERCIAL TEMPERATURE RANGES
R
t
W
WPF
t RFF
FF
t WFF DATA IN t DATA
OUT A
t
IN
DH
DATA
VALID
t DS DATA
OUT
VALID
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Figure 18. Write Data Flow-Through Mode
ORDERING INFORMATION
IDT XXXX Device Type X Power XX Speed X Package X Process/ Temperature Range
Blank
Commercial (0C to +70C)
P J
Plastic DIP Plastic Leaded Chip Carrier
20 25 35
Commercial Only Commercial Only Commercial Only
Access Time (tA) Speed in ns
L
Low Power
7208
65,536 x 9 FIFO
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